NDLI: Low-power high-accuracy timing systems for efficient duty cycling

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Low-power high-accuracy timing systems for efficient duty cycling

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Low-power high-accuracy timing systems for efficient duty cycling

Content Provider	ACM Digital Library
Author	Cho, Young H. Srivastava, Mani B. Schmid, Thomas Charbiwala, Zainul Friedman, Jonathan
Abstract	Time keeping and synchronization are important services for networked and embedded systems. High quality timing information allows embedded network nodes to provide accurate time-stamping, fast localization, efficient duty cycling schedules, and other basic but essential functions - all of which are required for low power operation. In this paper we present a new type of local clock source called Crystal Compensated Crystal based Timer (XCXT) and a number of novel algorithms that effectively utilize it to achieve low power consumption in wireless sensor networks. The XCXT has timing accuracies similar to timers based on temperature compensated crystal oscillators (TCXO) but has a lower implementation cost and requires less power. Our initial 8MHz prototype unit, using the simplest algorithm, achieves an effective frequency stability of ±1.2ppm and consumes only 1.27mW. On the other hand, commercially available TCXOs with similar stability can cost over 10 times as much and consume over 20mW. In addition to the prototype, we will present algorithms that will improve the XCXT's power consumption by at least 48%, depending on application and environmental conditions. We will also show how XCXT's power efficiency can be improved even further by employing clocks at different frequency when different time granularities are required by an application.
Starting Page	75
Ending Page	80
Page Count	6
File Format	PDF
ISBN	9781605581095
DOI	10.1145/1393921.1393943
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-08-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Low-power clocks Emulation Oscillator Time synchronization Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Low-power high-accuracy timing systems for efficient duty cycling

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