NDLI: Power delivery for high performance microprocessors

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Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits

Dynamic virtual ground voltage estimation for power gating

A multi-story power delivery technique for 3D integrated circuits

An expected-utility based approach to variation aware VLSI optimization under scarce information

Error-resilient low-power Viterbi decoders

Power management solutions for computer systems and datacenters

Power management from cores to datacenters: where are we going to get the next ten-fold improvements?

Caching for bursts (C-Burst): let hard disks sleep well and work energetically

Proactive temperature management in MPSoCs

Design of dual threshold voltages asynchronous circuits

A tutorial on test power

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension

Optimal power and noise allocation for analog and digital sections of a low power radio receiver

Penalty for power reduction -: performance or schedule or yield?

SOC designs in the energy conscious era

Clock gating for power optimization in ASIC design cycle theory & practice

Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling

A framework for energy consumption based design space exploration for wireless sensor nodes

Low power chips: a fabless asic perspective

Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures

Towards a green electronic world: a collaborative approach

Optimal technology selection for minimizing energy and variability in low voltage applications

A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops

Energy harvesting photodiodes with integrated 2D diffractive storage capacitance

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes

Increasing minimum operating voltage $(V_{DDmin})$ with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

Low power design under parameter variations

3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding

Entry control in network-on-chip for memory power reduction

$O^{2}C:$ occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

Power delivery for high performance microprocessors

Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors

Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies

Expected system energy consumption minimization in leakage-aware DVS systems

Full-system chip multiprocessor power evaluations using FPGA-based emulation

On leakage currents: sources and reduction for transistors, gates, memories and digital systems

Instruction-driven clock scheduling with glitch mitigation

System implications of integrated photonics

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology

Power-gating-aware high-level synthesis

Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation

Thermal analysis of 8-T SRAM for nano-scaled technologies

Energy conservation by adaptive feature loading for mobile content-based image retrieval

PowerAntz: distributed power sharing strategy for network on chip

Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes

On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers

Hybrid dynamic thermal management based on statistical characteristics of multimedia applications

Noninvasive leakage power tomography of integrated circuits by compressive sensing

Innovations to extend CMOS nano-transistors to the limit

Enhancing beneficial jitter using phase-shifted clock distribution

A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing

Low-power high-accuracy timing systems for efficient duty cycling

Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power

Analyzing static and dynamic write margin for nanometer SRAMs

Extending the lifetime of media recorders constrained by battery and flash memory size

Single stage static level shifter design for subthreshold to I/O voltage conversion

A secure and low-energy logic style using charge recovery approach

A 1-V piecewise curvature-corrected CMOS bandgap reference

Power-efficient clustering via incomplete bypassing

Advances in low power verification

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction

Variation-aware gate sizing and clustering for post-silicon optimized circuits

Power reduction in on-chip interconnection network by serialization

Word-interleaved cache: an energy efficient data cache architecture

A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning

Lazy instruction scheduling: keeping performance, reducing power

On the rules of low-power design (and how to break them)

A probabilistic technique for full-chip leakage estimation

Next-generation power-aware design

Bus encoding for simultaneous delay and energy optimization

Frequency planning for multi-core processors under thermal constraints

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Variability of flip-flop timing at sub-threshold voltages

Low power current mode receiver with inductive input impedance

Analytical results for design space exploration of multi-core processors employing thread migration

A physical level study and optimization of CAM-based checkpointed register alias table

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