NDLI: MITTS:memory inter-arrival time traffic shaping

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Asymmetry-aware work-stealing runtimes

Back to the future

Automatic generation of efficient accelerators for reconfigurable hardware

Opportunistic competition overhead reduction for expediting critical section in NoC based CMPs

Base-victim compression

Decoupling loads for nano-instruction set computers

The anytime automaton

All-inclusive ECC

Using multiple input, multiple output formal control to maximize resource efficiency in architectures

Boosting access parallelism to PCM-based main memory

Efficient synonym filtering and scalable delayed translation for hybrid virtual caching

Energy efficient architecture for graph analytics accelerators

Transparent offloading and mapping (TOM)

Short-circuit dispatch

Bit-plane compression

Production-run software failure diagnosis via adaptive communication tracking

Future vector microprocessor extensions for data aggregations

Accelerating markov random field inference using molecular optical gibbs sampling units

Rescuing uncorrectable fault patterns in on-chip memories through error pattern transformation

Exploiting dynamic timing slack for energy efficiency in ultra-low-power embedded systems

Towards statistical guarantees in controlling quality tradeoffs for approximate acceleration

Efficient synonym filtering and scalable delayed translation for hybrid virtual caching

ARM virtualization

Efficiently scaling out-of-order cores for simultaneous multithreading

Peak efficiency aware scheduling for highly energy proportional servers

Evaluation of an analog accelerator for linear algebra

RelaxFault memory repair

Energy efficient data encoding in DRAM channels exploiting data value similarity

Accelerating dependent cache misses with an enhanced memory controller

Power attack defense

Volume 44, Issue 2, May 2016

Volume 44, Issue 1, May 2016

MITTS:memory inter-arrival time traffic shaping

Content Provider	ACM Digital Library
Author	Zhou, Yanqi Wentzlaff, David
Abstract	Memory bandwidth severely limits the scalability and performance of multicore and manycore systems. Application performance can be very sensitive to both the delivered memory bandwidth and latency. In multicore systems, a memory channel is usually shared by multiple cores. Having the ability to precisely provision, schedule, and isolate memory bandwidth and latency on a per-core basis is particularly important when different memory guarantees are needed on a per-customer, per-application, or per-core basis. Infrastructure as a Service (IaaS) Cloud systems, and even general purpose multicores optimized for application throughput or fairness all benefit from the ability to control and schedule memory access on a fine-grain basis. In this paper, we propose MITTS (Memory Inter-arrival Time Traffic Shaping), a simple, distributed hardware mechanism which limits memory traffic at the source (Core or LLC). MITTS shapes memory traffic based on memory request inter-arrival time, enabling fine-grain bandwidth allocation. In an IaaS system, MITTS enables Cloud customers to express their memory distribution needs and pay commensurately. For instance, MITTS enables charging customers that have bursty memory traffic more than customers with uniform memory traffic for the same aggregate bandwidth. Beyond IaaS systems, MITTS can also be used to optimize for throughput or fairness in a general purpose multi-program workload. MITTS uses an online genetic algorithm to configure hardware bins, which can adapt for program phases and variable input sets. We have implemented MITTS in Verilog and have taped-out the design in a 25-core 32nm processor and find that MITTS requires less than 0.9% of core area. We evaluate across SPECint, PARSEC, Apache, and bhm Mail Server workloads, and find that MITTS achieves an average 1.18× performance gain compared to the best static bandwidth allocation, a 2.69× average performance/cost advantage in an IaaS setting, and up to 1.17× better throughput and 1.52× better fairness when compared to conventional memory bandwidth provisioning techniques.
Starting Page	532
Ending Page	544
Page Count	13
File Format	PDF
ISSN	01635964
DOI	10.1145/3007787.3001193
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	44
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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