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| Content Provider | ACM Digital Library |
|---|---|
| Author | Bachrach, Jonathan Kim, Donggyu Zimmer, Brian Izraelevitz, Adam Celio, Christopher Kim, Hokeun Lee, Yunsup Asanović, Krste |
| Abstract | This paper presents a sample-based energy simulation methodology that enables fast and accurate estimations of performance and average power for arbitrary RTL designs. Our approach uses an FPGA to simultaneously simulate the performance of an RTL design and to collect samples containing exact RTL state snapshots. Each snapshot is then replayed in gate-level simulation, resulting in a workload-specific average power estimate with confidence intervals. For arbitrary RTL and workloads, our methodology guarantees a minimum of four-orders-of-magnitude speedup over commercial CAD gate-level simulation tools and gives average energy estimates guaranteed to be within 5% of the true average energy with 99% confidence. We believe our open-source sample-based energy simulation tool Strober can not only rapidly provide ground truth for more abstract power models, but can enable productive design-space exploration early in the RTL design process. |
| Starting Page | 128 |
| Ending Page | 139 |
| Page Count | 12 |
| File Format | |
| ISSN | 01635964 |
| DOI | 10.1145/3007787.3001151 |
| Journal | ACM SIGARCH Computer Architecture News (CARN) |
| Volume Number | 44 |
| Issue Number | 3 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Energy Fpga Power estimation Hardware Modeling Statistical sampling |
| Content Type | Text |
| Resource Type | Article |
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