NDLI: A defect tolerant self-organizing nanoscale SIMD architecture (CARN, Vol. 34, Issue. 5)

Content Provider	ACM Digital Library
Author	Lebeck, Alvin R. Johri, Vijeta Patwardhan, Jaidev P. Dwyer, Chris
Abstract	The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing to the exponentially increasing cost of top-down lithography. Bottom-up manufacturing techniques, like self assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. Therefore, regardless of fabrication methodology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities.This paper explores a defect tolerant SIMD architecture. A key feature of our design is the ability of a large number of limited capability nodes with high defect rates (up to 30%) to self-organize into a set of SIMD processing elements. Despite node simplicity and high defect rates, we show that by supporting the familiar data parallel programming model the architecture can execute a variety of programs. The architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. On a medium sized system $(~1cm^{2}$ area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). For larger systems $(>1cm^{2}),$ the proposed architecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores.
Starting Page	241
Ending Page	251
Page Count	11
File Format	PDF
ISSN	01635964
DOI	10.1145/1168919.1168888
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	34
Issue Number	5
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Self-organizing Dna Bit-serial Simd Defect tolerance Nanocomputing Data parallel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A defect tolerant self-organizing nanoscale SIMD architecture (OPSR, Vol. 40, Issue. 5)

A defect tolerant self-organizing nanoscale SIMD architecture

A defect tolerant self-organizing nanoscale SIMD architecture (SIGP, Vol. 41, Issue. 11)

A self-organizing defect tolerant SIMD architecture

Routing in self-organizing nano-scale irregular networks

SIMD defragmenter:efficient ILP realization on data-parallel architectures (CARN, Vol. 40, Issue. 1)

A Defect Tolerant Self-Organizing Nanoscale SIMD Architecture (2006)

Ultra low-cost defect protection for microprocessor pipelines (CARN, Vol. 34, Issue. 5)

Tartan:evaluating spatial computation for whole program execution (CARN, Vol. 34, Issue. 5)

A defect tolerant self-organizing nanoscale SIMD architecture (CARN, Vol. 34, Issue. 5)

Similar Documents

A defect tolerant self-organizing nanoscale SIMD architecture (OPSR, Vol. 40, Issue. 5)

A defect tolerant self-organizing nanoscale SIMD architecture

A defect tolerant self-organizing nanoscale SIMD architecture (SIGP, Vol. 41, Issue. 11)

A self-organizing defect tolerant SIMD architecture

Routing in self-organizing nano-scale irregular networks

SIMD defragmenter:efficient ILP realization on data-parallel architectures (CARN, Vol. 40, Issue. 1)

A Defect Tolerant Self-Organizing Nanoscale SIMD Architecture (2006)

Ultra low-cost defect protection for microprocessor pipelines (CARN, Vol. 34, Issue. 5)

Tartan:evaluating spatial computation for whole program execution (CARN, Vol. 34, Issue. 5)

A defect tolerant self-organizing nanoscale SIMD architecture (CARN, Vol. 34, Issue. 5)