NDLI: iConn: A Communication Infrastructure for Heterogeneous Computing Architectures

Content Provider	ACM Digital Library
Author	Li, Zhongqi Goswami, Nilanjan Li, Tao
Copyright Year	2015
Abstract	Recently, the graphics processing unit (GPU) has made significant progress as a general-purpose parallel processor. The CPU and GPU cooperate together to solve data-parallel and control-intensive real-world applications in an optimized fashion. For example, emerging heterogeneous computing architectures such as Intel Sandy Bridge and AMD Fusion integrate the functionality of the CPU and GPU in a single die. However, the single-die CPU-GPU heterogeneous computing architecture faces the challenge of tight budget of die area. The conventional homogenous interconnect fails to provide satisfactory performance by fully exploiting the given area budget in the heterogeneous processing era. In this article, we aim to implement an interconnect network within an area budget for a CPU-GPU heterogeneous computing architecture. We propose iConn, a 2D mesh-style on-chip heterogeneous communication infrastructure. In iConn, a set of GPU logical units such as the stream processors, the texture units, and the rendering output units form a computing unit (CU). Differing from conventional homogenous router design, iConn adopts nonuniform on-chip routers in order to meet the unique communication demands from each single CPU and CU. The routers can also dynamically allocate their buffers across all virtual channels (VCs) to meet the latency requirements of CPUs and CUs. Moreover, the memory controller scheduling algorithm is modified from traditional load-over-store scheduling in order to prioritize the traffic. Our simulation results show that iConn improves the performance of CPUs by 23.0% and CUs by 9.4%.
Starting Page	1
Ending Page	23
Page Count	23
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2700238
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	11
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	CPU GPU Heterogeneous computing Network-on-chip
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Complex network-enabled robust wireless network-on-chip architectures

Architectural considerations for CPU and network interface integration

The GPU Computing Era

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor

Nanoarray architectures multilevel simulation

iConn: A Communication Infrastructure for Heterogeneous Computing Architectures

Similar Documents

Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Complex network-enabled robust wireless network-on-chip architectures

Architectural considerations for CPU and network interface integration

The GPU Computing Era

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor

Nanoarray architectures multilevel simulation

iConn: A Communication Infrastructure for Heterogeneous Computing Architectures