NDLI: Nanoarray architectures multilevel simulation

Content Provider	ACM Digital Library
Author	Frache, Stefano Graziano, Mariagrazia Zamboni, Maurizio
Copyright Year	2014
Abstract	Density and regularity are deemed as the major advantages of nanoarray architectures based on nanowires. Literature demonstrated that proper reliability analyzes must be performed and solutions have to be devised to improve nanoarrays yield. Their complexity and high-fault probability claim for specific design automation tools able to explore circuit solutions, performance and fault-tolerant approaches. We envision a simulator conceived to carry on characterizations in terms of logic behavior, defect-induced output error rate assessment, switching activity, power and timing performance. Though already existing for traditional technology, a simulator based on specific technological and topological tiled nanoarray descriptions, and conceived to join both device and architecture levels, has never been attempted at the degree of accuracy we present. Our contribution is twofold. First, marking a difference with respect to the state of the art, we developed an algorithm based on an event-driven engine which works at switch level and is not simply built on top of cost functions evaluations. The straightforward advantage is the possibility to follow the evolution of dynamic control sequences throughout all the inner components of the nanoarray, and, as a consequence, to obtain circuit level characterization as a projection of the real internal parameters. Second, we added to our simulator the capability to inject faults with specific statistical distributions associated to the nanoarray topology. Here we extract output error rates and yield for one of the possible nanoarray structures proposed in literature, the NASIC. Results specificity and accuracy demonstrate the simulator trustworthiness, its effectiveness for extensive nanoarrays characterization and its suitability as a foundation for both higher architectural and lower device simulation levels. The aim of this work, then, is to provide insights into the intertwined relation between actual technology and circuit design for these emerging fabrics, and, as a consequence, to clarify how defects and variability affect circuits and systems performance.
Starting Page	1
Ending Page	20
Page Count	20
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2541882
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	10
Issue Number	1
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design space exploration for 3D architectures

Evaluation of design strategies for stochastically assembled nanoarray memories

Design Considerations for Multilevel CMOS/Nano Memristive Memory

Evolving dependability

Guest editorial: IEEE/ACM symposium on nanoscale architectures (NANOARCH07)

Application-independent defect tolerance of reconfigurable nanoarchitectures

Low-overhead defect tolerance in crossbar nanoarchitectures

Toward a Sparse Self-Organizing Map for Neuromorphic Architectures

A Fast Extraction Algorithm for Defect-Free Subcrossbar in Nanoelectronic Crossbar

Nanoarray architectures multilevel simulation

Similar Documents

Design space exploration for 3D architectures

Evaluation of design strategies for stochastically assembled nanoarray memories

Design Considerations for Multilevel CMOS/Nano Memristive Memory

Evolving dependability

Guest editorial: IEEE/ACM symposium on nanoscale architectures (NANOARCH07)

Application-independent defect tolerance of reconfigurable nanoarchitectures

Low-overhead defect tolerance in crossbar nanoarchitectures

Toward a Sparse Self-Organizing Map for Neuromorphic Architectures

A Fast Extraction Algorithm for Defect-Free Subcrossbar in Nanoelectronic Crossbar

Nanoarray architectures multilevel simulation