NDLI: Complex network-enabled robust wireless network-on-chip architectures

Please wait, while we are loading the content...

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 13

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 12

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 11

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 10

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 9

Issue 4(Special Issue on Bioinformatics), November 2013

Issue 3, September 2013

Design of efficient reversible logic-based binary and BCD adder circuits

Color image processing with multi-peak resonant tunneling diodes

Cell transformations and physical design techniques for 3D monolithic integrated circuits

Design space exploration of FinFET cache

ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory

NBTI-aware circuit node criticality computation

Complex network-enabled robust wireless network-on-chip architectures

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis

Issue 2(Special issue on memory technologies), May 2013

Issue 1, February 2013

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 8

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 7

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 6

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 5

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 4

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 3

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 2

ACM Journal on Emerging Technologies in Computing Systems (JETC) : Volume 1

Complex network-enabled robust wireless network-on-chip architectures

Content Provider	ACM Digital Library
Author	Wettin, Paul Vidapalapati, Anuroop Ganguly, Amlan Pande, Partha Pratim
Copyright Year	2013
Abstract	The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon NanoTube (CNT) antennas are shown to outperform traditional wire-based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies will be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This article advocates adoption of such complex network-based architectures to minimize the effect of wireless link failures on the performance of the NoC. Through cycle-accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of high degrees of link failures. We demonstrate the robustness of the proposed wireless NoC architecture by incorporating both uniform and application-specific traffic patterns.
Starting Page	1
Ending Page	19
Page Count	19
File Format	PDF
ISSN	15504832
e-ISSN	15504840
DOI	10.1145/2491676
Journal	ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number	9
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-10-08
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Multicore NoC Carbon nanotube Fault tolerance Small world Wireless links
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Nanoscience and Nanotechnology Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Complex network inspired fault-tolerant NoC architectures with wireless links

A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures

Complex network inspired fault-tolerant NoC architectures with wireless links

Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC

A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

CDMA Enabled Wireless Network-on-Chip

Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach

Complex network-enabled robust wireless network-on-chip architectures

Similar Documents

Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Complex network inspired fault-tolerant NoC architectures with wireless links

A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures

Complex network inspired fault-tolerant NoC architectures with wireless links

Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC

A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

CDMA Enabled Wireless Network-on-Chip

Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach

Complex network-enabled robust wireless network-on-chip architectures