NDLI: A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

Issue 4(Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015), September 2016

Issue 3(Special Issue on Reconfigurable Components with Source Code), September 2016

Introduction to Special Issue on Reconfigurable Components with Source Code

Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs

The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator

Modular Switched Multiported SRAM-Based Memories

A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

Optimizing Soft Vector Processing in FPGA-Based Embedded Systems

Hardware Accelerated Alignment Algorithm for Optical Labeled Genomes

Issue 2(Special Section on RAW2014), February 2016

Issue 1(Special Section on the 2014 International Symposium on Applied Reconfigurable Computing), November 2015

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

Content Provider	ACM Digital Library
Author	Schwartz, Eric Cooke, Patrick Stitt, Greg
Copyright Year	2016
Abstract	Sliding-window applications, an important class of the digital-signal processing domain, are highly amenable to pipeline parallelism on field-programmable gate arrays (FPGAs). Although memory bandwidth often restricts parallelism for many applications, sliding-window applications can leverage custom buffers, referred to as sliding-window generators, that provide massive input bandwidth that far exceeds the capabilities of external memory. Previous work has introduced a variety of sliding-window generators, but those approaches typically generate at most one window per cycle, which significantly restricts parallelism. In this article, we address this limitation with a parallel sliding-window generator that can generate a configurable number of windows every cycle. Although in practice the number of parallel windows is limited by memory bandwidth, we show that even with common bandwidth limitations, the presented generator enables near-linear speedups up to 16x faster than previous FPGA studies that generate a single window per cycle, which were already in some cases faster than graphics-processing units and microprocessors.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2800789
Volume Number	9
Issue Number	3
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-05-20
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA Parallelism Pipelining Sliding-window applications
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

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