NDLI: Optimizing Soft Vector Processing in FPGA-Based Embedded Systems

Please wait, while we are loading the content...

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

Issue 4(Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015), September 2016

Issue 3(Special Issue on Reconfigurable Components with Source Code), September 2016

Introduction to Special Issue on Reconfigurable Components with Source Code

Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs

The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator

Modular Switched Multiported SRAM-Based Memories

A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

Optimizing Soft Vector Processing in FPGA-Based Embedded Systems

Hardware Accelerated Alignment Algorithm for Optical Labeled Genomes

Issue 2(Special Section on RAW2014), February 2016

Issue 1(Special Section on the 2014 International Symposium on Applied Reconfigurable Computing), November 2015

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

Optimizing Soft Vector Processing in FPGA-Based Embedded Systems

Content Provider	ACM Digital Library
Author	Kapre, Nachiket
Copyright Year	2016
Abstract	Soft vector processors can augment and extend the capability of FPGA-based embedded systems-on-chip such as the Xilinx Zynq. However, configuring and optimizing the soft processor for best performance is hard. We must consider architectural parameters such as precision, vector lane count, vector length, chunk size, and DMA scheduling to ensure efficient execution of code on the soft vector processing platform. To simplify the design process, we develop a compiler framework and an autotuning runtime that splits the optimization into a combination of static and dynamic passes that map data-parallel computations to the soft processor. We compare and contrast implementations running on the scalar ARM processor, the embedded NEON hard vector engine, and low-level streaming Verilog designs with the VectorBlox MXP soft vector processor. Across a range of data-parallel benchmarks, we show that the MXP soft vector processor can outperform other organizations by up to 4 × while saving ≈ 10% dynamic power. Our compilation and runtime framework is also able to outperform the gcc NEON vectorizer under certain conditions by explicit generation of NEON intrinsics and performance tuning of the autogenerated data-parallel code. When constrained by IO bandwidth, soft vector processors are even competitive with spatial Verilog implementations of computation.
Starting Page	1
Ending Page	17
Page Count	17
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2912884
Volume Number	9
Issue Number	3
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-05-20
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Vector processors Soft processors Streaming computations
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Vector Processing as a Soft Processor Accelerator

A Compiler for an Array and Vector Processing Language

Portable, Flexible, and Scalable Soft Vector Processors

Scalable, vector processors for embedded systems

Experiences teaching an FPGA-based embedded systems class

FPGA-based hardware accelerator for high-performance data-stream processing

VESPA: portable, scalable, and flexible FPGA-based vector processors

Energy-Efficient Computations on FPGAs

Fpga-based soft vector processors (2009).

Optimizing Soft Vector Processing in FPGA-Based Embedded Systems

Similar Documents

Vector Processing as a Soft Processor Accelerator

A Compiler for an Array and Vector Processing Language

Portable, Flexible, and Scalable Soft Vector Processors

Scalable, vector processors for embedded systems

Experiences teaching an FPGA-based embedded systems class

FPGA-based hardware accelerator for high-performance data-stream processing

VESPA: portable, scalable, and flexible FPGA-based vector processors

Energy-Efficient Computations on FPGAs

Fpga-based soft vector processors (2009).

Optimizing Soft Vector Processing in FPGA-Based Embedded Systems