NDLI: Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Please wait, while we are loading the content...

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Content Provider	ACM Digital Library
Author	Zhai, Antonia Yew, Pen-Chung Holey, Anup Mekkat, Vineeth
Copyright Year	2015
Abstract	Heterogeneous multicore processors that integrate CPU cores and data-parallel accelerators such as graphic processing unit (GPU) cores onto the same die raise several new issues for sharing various on-chip resources. The shared last-level cache (LLC) is one of the most important shared resources due to its impact on performance. Accesses to the shared LLC in heterogeneous multicore processors can be dominated by the GPU due to the significantly higher number of concurrent threads supported by the architecture. Under current cache management policies, the CPU applications’ share of the LLC can be significantly reduced in the presence of competing GPU applications. For many CPU applications, a reduced share of the LLC could lead to significant performance degradation. On the contrary, GPU applications can tolerate increase in memory access latency when there is sufficient thread-level parallelism (TLP). In addition to the performance challenge, introduction of diverse cores onto the same die changes the energy consumption profile and, in turn, affects the energy efficiency of the processor. In this work, we propose heterogeneous LLC management (HeLM), a novel shared LLC management policy that takes advantage of the GPU’s tolerance for memory access latency. HeLM is able to throttle GPU LLC accesses and yield LLC space to cache-sensitive CPU applications. This throttling is achieved by allowing GPU accesses to bypass the LLC when an increase in memory access latency can be tolerated. The latency tolerance of a GPU application is determined by the availability of TLP, which is measured at runtime as the average number of threads that are available for issuing. For a baseline configuration with two CPU cores and four GPU cores, modeled after existing heterogeneous processor designs, HeLM outperforms least recently used (LRU) policy by 10.4%. Additionally, HeLM also outperforms competing policies. Our evaluations show that HeLM is able to sustain performance with varying core mix. In addition to the performance benefit, bypassing also reduces total accesses to the LLC, leading to a reduction in the energy consumption of the LLC module. However, LLC bypassing has the potential to increase off-chip bandwidth utilization and DRAM energy consumption. Our experiments show that HeLM exhibits better energy efficiency by reducing the $ED^{2}$ by 18% over LRU while impacting only a 7% increase in off-chip bandwidth utilization.
Starting Page	1
Ending Page	29
Page Count	29
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/2710019
Volume Number	12
Issue Number	1
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-03-09
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Heterogeneous multicore Bypassing Cache management policy Last-level cache
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Managing shared last-level cache in a heterogeneous multicore processor

Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache

Locality-aware data replication in the last-level cache for large scale multicores

Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System

Last level cache size heterogeneity in embedded systems

Quality of service shared cache management in chip multiprocessor architecture

Lightweight dynamic partitioning for last-level cache of multicore processor on real system

Exploiting reuse locality on inclusive shared last-level caches

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Similar Documents

Managing shared last-level cache in a heterogeneous multicore processor

Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache

Locality-aware data replication in the last-level cache for large scale multicores

Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System

Last level cache size heterogeneity in embedded systems

Quality of service shared cache management in chip multiprocessor architecture

Lightweight dynamic partitioning for last-level cache of multicore processor on real system

Exploiting reuse locality on inclusive shared last-level caches

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor