NDLI: $\textit{SPMCloud}:$ Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud

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SPMCloud: Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud

MAESTRO— Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs

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$\textit{SPMCloud}:$ Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud

Content Provider	ACM Digital Library
Author	Bathen, Luis Angel D. Dutt, Nikil D.
Copyright Year	2014
Abstract	The era of cloud computing on-a-chip is enabled by the aggressive move towards many-core platforms and the rapid adoption of Network-on-Chips. As a result, there is a need for large-scale distributed on-chip shared memories that are reliable, low power, and seamlessly manageable. In this work, we propose $\textit{SPMCloud},$ a novel scratchpad-memory-based cloud-inspired volatile storage subsystem designed to meet the needs of future-generation many-core platforms. $\textit{SPMCloud}$ is composed of several concepts, including: (1) a highly scalable data-center-like memory subsystem that exploits two enterprise-network-inspired memory configurations, namely, embedded Network Attached Storage $(\textit{eNAS})$ and embedded Storage Area Network $(\textit{eSAN}),$ and (2) on-demand allocation of reliable memory space through memory virtualization and the use of embedded RAIDs. Our experimental results on Mediabench/CHStone benchmarks show that the $\textit{SPMCloud}'s$ fully distributed reliable memory subsystems can achieve 48% energy savings and 70% latency reduction on average over state-of-the-art NoC memory reliability techniques. We then evaluate the scalability of the $\textit{SPMCloud}$ and compare it with traditional SPM allocation policies. The $\textit{SPMCloud}'s$ dynamic allocator outperforms the best competition by an average 60% $(\textit{eNAS})$ and 46% $(\textit{eSAN})$ when the platform runs at 250 MHz and by an average 80% $(\textit{eNAS})$ and 40% when running at 1 GHz. Moreover, the $\textit{SPMCloud}$ achieves an average 83% energy savings across all configurations (number of cores) with respect to the best competitors when running at 250 MHz and 1 GHz. We then studied the SPM hit ratio across the various allocation policies discussed in this article and showed that on average the $\textit{SPMCloud}'s$ priority-driven dynamic allocation policy achieves 93.5% SPM hit ratio, 0.6% higher hit ratio than the closest allocation policy. We then showed that the $\textit{eNAS}$ and $\textit{eSAN}$ achieve an average of 67.9% and 29% reduction in execution time, respectively, over the best competitor. Similarly, the $\textit{eNAS}$ and $\textit{eSAN}$ achieve an average of 82.7% and 82.3% energy savings, respectively, over the best competitor. Furthermore, we evaluated the scalability of the $\textit{SPMCloud}$ and its performance/energy efficiency when providing support for some of the heavier E-RAID levels, and showed that the $\textit{eNAS}/\textit{eSAN}$ configurations with SECDED achieve an average of 51.5% and 34.9% reduction in execution time, respectively, over the best competitor with SECDED. Similarly, the $\textit{eNAS}/\textit{eSAN}$ configurations with E-RAID Level 1, + SECDED achieve an average of 82.3% and 75.6% energy savings, respectively, over the best competitor.
Starting Page	1
Ending Page	45
Page Count	45
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2611755
Volume Number	19
Issue Number	3
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-06-23
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Network-on-chip Distributed memories Many-core platforms Reliability Virtualization
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors

SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

SPMVisor: Dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories

CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management

A lightweight VMM on many core for high performance computing

A data acquisition methodology for on-chip repair of embedded memories

A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms

HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories

$\textit{SPMCloud}:$ Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud

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$\textit{SPMCloud}:$ Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud