NDLI: A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms

Content Provider	IEEE Xplore Digital Library
Author	Anh Thien Tran Dean Nguyen Truong Baas, B.
Copyright Year	1982
Abstract	This paper presents a globally-asynchronous locally-synchronous (GALS)-compatible circuit-switched on-chip network that is well suited for use in many-core platforms targeting streaming digital signal processing and embedded applications which typically have a high degree of task-level parallelism among computational kernels. Inter-processor communication is achieved through a simple yet effective reconfigurable source-synchronous network. Interconnect paths between processors can sustain a peak throughput of one word per cycle. A theoretical model is developed for analyzing the performance of the network. A 65 nm complementary metal-oxide-semiconductor GALS chip utilizing this network was fabricated which contains 164 programmable processors, three accelerators and three shared memory modules. For evaluating the efficiency of this platform, a complete 802.11a wireless local area network baseband receiver was implemented. It has a real-time throughput of 54 Mb/s with all processors running at 594 MHz and 0.95-V, and consumes an average of 174.8 mW with 12.2 mW (or 7.0%) dissipated by its interconnect links and switches. With the chip's dual supply voltages set at 0.95-V and 0.75-V, and individual processors' oscillators operating at workload-based optimal frequencies, the receiver consumes 123.2 mW, which is a 29.5% reduction in power. Measured power consumption values from the chip are within 2-5% of the estimated values.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	897
Ending Page	910
Page Count	14
File Size	6588649
File Format	PDF
ISSN	02780070
Volume Number	29
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Integrated circuit interconnections Throughput Digital signal processing Parallel processing Computer networks Concurrent computing Embedded computing Kernel Performance analysis source-synchronous 2-D mesh digital signal processing (DSP) embedded globally-asynchronous locally-synchronous (GALS) interconnect many-core chip network on-chip programmable reconfigurable
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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