NDLI: Transistor placement for noncomplementary digital VLSI cell synthesis

Content Provider	ACM Digital Library
Author	Sakallah, Karem A. Riepe, Michael A.
Copyright Year	2003
Abstract	There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing. Traditional digital cell layout synthesis tools derived from the highly stylized "functional cell" style break down when confronted with such circuit topologies. These cells require a full-custom, two-dimensional layout style which currently requires skilled manual design. In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts. We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains. The primary mechanism for supporting this concurrent optimization is the placement of transistor subchains, diffusion-break-free components of the full transistor chains. When a chain is reordered, transistors may move from one subchain (and therefore one placement component) to another. We will demonstrate how this permits the chain ordering to be optimized for both intra-chain and inter-chain routing. We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool. These experiments make use of a new set of benchmark circuits which provide a rich sample of representative examples in several noncomplementary digital logic families.
Starting Page	81
Ending Page	107
Page Count	27
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/606603.606608
Volume Number	8
Issue Number	1
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Cell Synthesis Euler graphs Benchmark circuits Digital circuits Noncomplementary circuits Sequence pair optimization Transistor chaining Transistor placement
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Gravity: Fast placement for 3-D VLSI

Fast placement approaches for FPGAs

Rectilinear block placement using B*-trees

VLSI/PCB placement with obstacles based on sequence pair

Combinatorial techniques for mixed-size placement

Delay optimization of digital CMOS VLSI circuits by transistor reordering

Power-delay optimizations in gate sizing

A fast transistor-chaining algorithm for CMOS cell layout

Postlayout optimization for synthesis of Domino circuits

Transistor placement for noncomplementary digital VLSI cell synthesis

Similar Documents

Gravity: Fast placement for 3-D VLSI

Fast placement approaches for FPGAs

Rectilinear block placement using B*-trees

VLSI/PCB placement with obstacles based on sequence pair

Combinatorial techniques for mixed-size placement

Delay optimization of digital CMOS VLSI circuits by transistor reordering

Power-delay optimizations in gate sizing

A fast transistor-chaining algorithm for CMOS cell layout

Postlayout optimization for synthesis of Domino circuits

Transistor placement for noncomplementary digital VLSI cell synthesis