NDLI: Confidence analysis for defect-level estimation of VLSI random testing

Content Provider	ACM Digital Library
Author	Jone, Wen-Ben Tsai, K. S.
Copyright Year	1998
Abstract	The defect level in circuit testing is the percentage of circuits such as chips, that are defective and shipped for use after testing. Our previously published results showed that the defect level of circuit fabrication and testing should be a probability distribution, rather than a single value, and the concept of confidence degree was proposed [Gondalia et al. 1993; Jone et al. 1995]. In this work, defect level is represented by a confidence interval which is more conventional and easier to interpret. The point estimate of defect level analysis and conditions to avoid meaningless confidence intervals are also investigated. Methods for adaptive random test length determination driven by different confidence intervals or interval length are proposed to meet both test requirements and test costs tradeoff. Finally, a complete test plan that can direct the test flow from fabrication infancy to maturity is suggested.
Starting Page	389
Ending Page	407
Page Count	19
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/293625.293629
Volume Number	3
Issue Number	3
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1998-07-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	VLSI testing Defect level analysis Random testing Test confidence analysis Test quality
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

$I_{DDX}-based$ test methods: A survey

Test chip experimental results on high-level structural test

Gate-level test generation for sequential circuits

Recent developments in high-level synthesis

Instruction-level test methodology for CPU core self-testing

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis

Analysis of FPGA/FPIC switch modules

Realizing a high measure of confidence for defect level analysis of random testing [VLSI]

Combinatorial techniques for mixed-size placement

Confidence analysis for defect-level estimation of VLSI random testing

Similar Documents

$I_{DDX}-based$ test methods: A survey

Test chip experimental results on high-level structural test

Gate-level test generation for sequential circuits

Recent developments in high-level synthesis

Instruction-level test methodology for CPU core self-testing

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis

Analysis of FPGA/FPIC switch modules

Realizing a high measure of confidence for defect level analysis of random testing [VLSI]

Combinatorial techniques for mixed-size placement

Confidence analysis for defect-level estimation of VLSI random testing