NDLI: A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Content Provider	Springer Nature Link
Author	Ferreira, Ricardo Denver, Waldir Pereira, Monica Wong, Stephan Lisbȏa, Carlos A. Carro, Luigi
Copyright Year	2015
Abstract	In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code on-the-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.
Starting Page	45
Ending Page	66
Page Count	22
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	85
Issue Number	1
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2015-02-17
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Modulo scheduling Binary translation Run-time Coarse-grained reconfigurable accelerator Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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