NDLI: Designing Run-Time Reconfigurable Systems with JHDL

Content Provider	Springer Nature Link
Author	Bellows, Peter Hutchings, Brad
Copyright Year	2001
Abstract	Run-time reconfigurable (RTR) systems are FPGA-based systems that reconfigure FPGAs during execution to alter hardware organization and composition to meet the varying needs of applications as they execute. These systems are difficult to describe with conventional tools (schematic capture, VHDL synthesis, etc.) because most tools assume that the underlying hardware organization is static. JHDL is a Java-based design environment capable of describing, netlisting, simulating and executing complex, dynamic RTR systems. Using conventional Java syntax, users describe hardware structures as objects; as these hardware-object constructors are invoked, JHDL automatically configures hardware circuits onto FPGA hardware, thus directly supporting the dynamic nature of RTR systems with standard language constructs. JHDL also supports codesign of the software and hardware parts of the system; in other words, the entire application can be described in a single piece of Java code that can be co-simulated/co-executed with the FPGA hardware. To date, RTR design with JHDL has focused on the development of automated target recognition (ATR) systems, and working systems described in JHDL have been demonstrated.
Starting Page	29
Ending Page	45
Page Count	17
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	28
Issue Number	1-2
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2001-05-01
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

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