NDLI: Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Content Provider	Springer Nature Link
Author	Sau, Carlo Meloni, Paolo Raffo, Luigi Palumbo, Francesca Bezati, Endri Casale Brunet, Simone Mattavelli, Marco
Copyright Year	2015
Abstract	The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.
Starting Page	143
Ending Page	165
Page Count	23
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	85
Issue Number	1
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2015-08-15
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	MPEG-RVC Dataflow Coarse-grained reconfiguration Multi-functional Multi-mode RVC MPEG-4 SP decoder RVC Intra MPEG-4 SP JPEG codec ITU-T.IS 1091 MDC Xronos TURNUS Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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