NDLI: A Hardware/Software Co-Design of MP3 Audio Decoder

Content Provider	Springer Nature Link
Author	Tsai, Tsung Han Yang, Ya Chau Liu, Chun Nan
Copyright Year	2005
Abstract	The Moving Picture Experts Group (MPEG) audio coding standard offers three levels of compression algorithms where the MPEG Layer III (MP3) has the best quality but with the most complexity. There are several complex coding techniques involved in MP3 audio decoding algorithm, therefore, it is difficult to make an efficient architecture design. This paper presents a hardware/software co-design method for the implementation of MP3 audio decoder, which meets the real-time requirement of MP3 standard. The software and hardware part of this decoder is partitioned into a pre-processing and a post-processing unit respectively. The pre-processing unit with a programmable parser processor is developed for the implementation of intensive decision making operations needed for audio bitstreams. The post-processing unit with a dedicated hardware of modified fast algorithm is designed for the regular and computation-intensive operations in MP3 audio decoding flow. The architecture achieves a high throughput with a reduced memory requirement and hardware complexity. With a two-level pipeline approach, it allows a high hardware utilization and is suitable to low power implementation. The proposed decoder system has been designed and implemented using VLSI cell-based approach. The die size is 3.5 × 4.45 mm$^{2}$ with the maximum operation frequency of 20 MHz.
Starting Page	111
Ending Page	127
Page Count	17
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	41
Issue Number	1
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2005-08-01
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	MPEG MP3 Co-Design IMDCT Filterbank DSP VLSI ASIC Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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