NDLI: An Efficient Picture-Rate Up-Converter

Content Provider	Springer Nature Link
Author	Berić, Aleksandar Haan, Gerard de Sethuraman, Ramanathan Meerbergen, Jef van
Copyright Year	2005
Abstract	The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this work, we analyze and optimize algorithm and architecture of a picture rate up-conversion module. We perform algorithm/architecture co-design in which we meet high quality specification while keeping the power dissipation low. In the algorithm front, we focus on the motion estimation which is computationally the most intensive part of the picture-rate up-conversion application. We analyze the following parameters of the motion estimation algorithm: The number of motion estimation iterations per input image pair and the image scanning order of individual iterations. Further, we apply novel pre-processing technique to address the issue of reducing the already extremely low number of motion vector candidate evaluations. However, optimal selection of motion vector candidates is a necessity to achieve high picture quality. In the architectural front, to cope with the large memory bandwidth requirements of the application, we use multi-level caching to exploit locality of reference. Further, we apply data compression to the image data stored in memory, to reduce the memory capacity and bandwidth requirements. Both the above techniques significantly reduce the overall power dissipation.
Starting Page	49
Ending Page	63
Page Count	15
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	41
Issue Number	1
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2005-08-01
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	picture-rate up-converter low-power motion estimation motion compensation Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Low Power Architecture for HASM Motion Tracking

A New Efficient Block-Matching Algorithm for Motion Estimation

Motion Estimation for Video Coding Standards

Instruction Scheduling for Low Power

A Flexible 200 GOPS HDTV Motion Estimation Chip

Low Power Motion Estimation Design Based on Non-Uniform Pixel Truncation

Methodical Low-Power ASIP Design Space Exploration

Low Power Digital Frequency Conversion Architectures

Low-Power Constant-Coefficient Multiplier Generator

An Efficient Picture-Rate Up-Converter

Similar Documents

A Low Power Architecture for HASM Motion Tracking

A New Efficient Block-Matching Algorithm for Motion Estimation

Motion Estimation for Video Coding Standards

Instruction Scheduling for Low Power

A Flexible 200 GOPS HDTV Motion Estimation Chip

Low Power Motion Estimation Design Based on Non-Uniform Pixel Truncation

Methodical Low-Power ASIP Design Space Exploration

Low Power Digital Frequency Conversion Architectures

Low-Power Constant-Coefficient Multiplier Generator

An Efficient Picture-Rate Up-Converter