NDLI: Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration

Content Provider	Springer Nature Link
Author	Panainte, Elena Moscu Bertels, Koen Vassiliadis, Stamatis
Copyright Year	2006
Abstract	In this paper, we study the performance impact of dynamic hardware reconfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the “FPGA-area placement conflicts” between the available hardware configurations. The presented algorithm allows the anticipation of hardware configuration instructions up to the application’s main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed hardware configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable hardware execution.
Starting Page	161
Ending Page	172
Page Count	12
File Format	PDF
ISSN	09225773
Journal	Journal of Signal Processing Systems
Volume Number	43
Issue Number	2-3
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2006-06-01
Publisher Place	Boston
Access Restriction	Subscribed
Subject Keyword	reconfigurable computing compiler optimization reconfiguration overhead Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Image Processing and Computer Vision Pattern Recognition Computer Imaging, Vision, Pattern Recognition and Graphics
Content Type	Text
Resource Type	Article
Subject	Signal Processing Information Systems Electrical and Electronic Engineering

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