NDLI: An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization

Content Provider	Springer Nature Link
Author	Chang, Yun Nan Tong, Ting Chi
Copyright Year	2008
Abstract	In this paper, a highly efficient inter-interpolation architecture for the H.264/AVC standard is proposed. Since the placement order of frame pixels in the memory is either row-wise or column-wise which may not be suitable for the sample prediction in particular direction, this paper proposes a novel interpolator design which can dynamically configure the data-path for different predicted modes to perform proper computation schedules suitable for the nature input order of reference samples. The proposed design methodology not only can avoid the additional data transposition buffer, but most importantly the data transfer time spent to fetch the reference samples can be overlapped with the data computation time. Furthermore, by decomposing the chroma interpolation into a series of shift and addition operations, both luma and chroma interpolations can be integrated within the same module. In addition to the data-path design, this paper also proposes a new data-reuse buffer design based on a two-dimensional cache architecture to explore the possible data reuse among the inter and intra partitions. This design can be easily integrated with the H.264 interpolator to reduce the enormous demand of memory access. Our experimental results shows that our saving of memory bandwidth can be 23% more than what the best design can achieve by exploring the intra-partition data reuse only. The proposed design methodology has been implemented, and the result shows that the proposed interpolation architecture is the most compact design among the literatures which can perform the real-time H.264 video decoding with resolution up to 1920×1088 high-definition television standard. The proposed interpolator can be applied to the dedicated H.264 hardware codec design for various consumer devices.
Starting Page	435
Ending Page	448
Page Count	14
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	53
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2008-07-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	H.264 Inter-interpolation Motion compensation Chroma interpolation Luma interpolation Inter-partition Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Image Processing and Computer Vision Electronic and Computer Engineering Circuits and Systems Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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