NDLI: Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Content Provider	Springer Nature Link
Author	Ho, H. Szwarc, V. Kwasniewski, T.
Copyright Year	2010
Abstract	A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.
Starting Page	353
Ending Page	365
Page Count	13
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	61
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2010-03-06
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Variable multiplication CSE Bit slice Low complexity Reconfigurable circuit Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Image Processing and Computer Vision Electrical Engineering Circuits and Systems Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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