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| Content Provider | Springer Nature Link |
|---|---|
| Author | Gal, Bertrand Casseau, Emmanuel |
| Copyright Year | 2010 |
| Abstract | Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word-length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC. |
| Starting Page | 341 |
| Ending Page | 357 |
| Page Count | 17 |
| File Format | |
| ISSN | 19398018 |
| Journal | Journal of Signal Processing Systems |
| Volume Number | 62 |
| Issue Number | 3 |
| e-ISSN | 19398115 |
| Language | English |
| Publisher | Springer US |
| Publisher Date | 2010-04-07 |
| Publisher Place | Boston |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Data sizing Hardware design High-level synthesis Resource sharing Pattern Recognition Electrical Engineering Circuits and Systems Computer Imaging, Vision, Pattern Recognition and Graphics Image Processing and Computer Vision Signal, Image and Speech Processing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture |
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