NDLI: Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Content Provider	Springer Nature Link
Author	Lin, Tay Jyi Chen, Shin Kai Kuo, Yu Ting Liu, Chih Wei Hsiao, Pi Chen
Copyright Year	2007
Abstract	This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1∼26.0%. The DSP has been fabricated in the UMC 0.13 μm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 × 3.15 mm$^{2}$ including 160 KB on-chip SRAM.
Starting Page	209
Ending Page	223
Page Count	15
File Format	PDF
ISSN	19398018
Journal	Journal of Signal Processing Systems
Volume Number	51
Issue Number	3
e-ISSN	19398115
Language	English
Publisher	Springer US
Publisher Date	2007-08-20
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	VLIW digital signal processor register organization instruction encoding micro-architecture Computer Imaging, Vision, Pattern Recognition and Graphics Pattern Recognition Image Processing and Computer Vision Electronic and Computer Engineering Circuits and Systems Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Signal Processing Control and Systems Engineering Information Systems Modeling and Simulation Hardware and Architecture

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