NDLI: Silicon-on-insulator non-volatile memories with second-bit effect

Content Provider	Springer Nature Link
Author	Perniola, L. Iannaccone, G.
Copyright Year	2006
Abstract	In this paper we propose an analytical approach to investigate the electrostatic impact of very small charged regions in the gate dielectric of dual bit non-volatile memories (NVMs) Silicon-On-Insulator (SOI) cells. This original model is based on the surface potential approach and allows to investigate the behavior of NVMs in subthreshold working condition. It is particularly accurate for charged region, as small as L $_{2}$ = 10 nm and up to a charge density of Q = 10$^{13}$ cm$^{−2}$ and it is complementarity to another approach proposed for bulk devices [1]. Relevant consequences of the asymmetric charging of the storage layer on the electrical characteristics of discrete-trap memories are thoroughly analyzed: the importance of Short Channel Effects (SCEs) for the performance of these cells is highlighted. Moreover a method for extracting an “effective” distribution of charges from the transfer characteristics is derived.
Starting Page	137
Ending Page	142
Page Count	6
File Format	PDF
ISSN	15698025
Journal	Journal of Computational Electronics
Volume Number	5
Issue Number	2-3
e-ISSN	15728137
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2006-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Mathematical and Computational Physics ApplicationMathematics/Computational Methods of Engineering Mechanical Engineering Optical and Electronic Materials Electronic and Computer Engineering
Content Type	Text
Resource Type	Article
Subject	Atomic and Molecular Physics, and Optics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering Modeling and Simulation

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