NDLI: A low-glitch binary-weighted DAC with delay compensation scheme

Content Provider	Springer Nature Link
Author	Chou, Fang Ting Chen, Chia Min Hung, Chung Chih
Copyright Year	2014
Abstract	This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable-delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transitions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 Ω termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respectively. The proposed DAC can be used in various applications in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 μm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.
Starting Page	277
Ending Page	289
Page Count	13
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	79
Issue Number	2
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2014-02-05
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Digital-to-analog converter (DAC) Glitch reduction Binary-weighted Current-steering DAC Circuits and Systems Electrical Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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