Loading...
Please wait, while we are loading the content...
Similar Documents
Vlsi Implementation of L 2 Memory Design for 3-d Integration
| Content Provider | Semantic Scholar |
|---|---|
| Author | Harsha, Gade Narayana Sri Anjaneeyulu, S. |
| Copyright Year | 2016 |
| Abstract | Recently, three-dimensional integration technology has allowed researchers and designers to explore novel architectures for computing systems. Due to the memory-intensive nature of signal processing systems, DSPs can greatly benefit from 3D memory integration technology realized by vertically stacking high-density memory below processing cores. In this paper, we analyze the energy and performance impacts of 3D memory integration in DSP systems by exploring a wide variety of memory configurations the technology enables. Large required size, and tolerance to latency and variations in memory access time make L2 memory a suitable option for 3-D integration. In this paper, we present a synthesizable 3-D-stackable L2 memory IP component, which can be attached to a cluster-based multicore platform through its network-on-chip interfaces offering highbandwidth memory access with low average latency. Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture based on low latency logarithmic interconnects, which allows stacking of multiple identical memory dies (MDs), supports multiple outstanding transactions, and achieves high clock frequencies due to its highly pipelined nature. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijesr.org/admin/upload_journal/journal_G.Sri%20Harsha%20%204may16esr.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
