NDLI: Architecture Design and VLSI Implementation of the Re-conf1gurable 2-D CAT/ICAT Chip for the Applications of Image Compression

Content Provider	IEEE Xplore Digital Library
Author	Rong-Jian Chen Wen-Kai Lu Jui-Lin Lai
Copyright Year	2007
Description	Author affiliation: Nat. United Univ., Miaoli (Rong-Jian Chen)
Abstract	Architecture design and VLSI implementation of the re-configurable 2-D CAT/ICAT chip for developing the CAT wavelets-based image coding system is presented in this paper. To facilitate the development of this CAT/ICAT chip, we firstly develop the evolution of CA to produce orthogonal 1-D CA bases; then we use the canonical product circuit to produce 2-D CA bases; finally, it utilizes input data and 2-D CA bases to produce 2-D CAT/ICAT coefficients. In order to enhance the flexibility of applications, we developed the re-configurable 2-D CAT/ICAT circuit to make the proposed chip to produce 2-D 4 x 4, 8 x 8, and 16 x 16 CAT/ICAT coefficients. Throughputs of the 2-D 8 x 8, and 16 x 16 CAT/ICAT coefficients are same as that of 2-D 4 x 4 CAT/ICAT coefficients due to the proposed re-configurable 2-D CAT/ICAT chip has highly parallel processing property. We have accomplished the circuit synthesis using the SYNOPSYS tolls with the UMC 0.18 um Cell-library. The chip size was 12.888 mm , and the maximum operation frequency was 111MHz with 851mW total dynamic power. It shows that the architecture of the proposed re-configurable 2-D CAT/ICAT chip is suitable for VLSI realization .
Starting Page	1
Ending Page	6
File Size	3210044
Page Count	6
File Format	PDF
ISBN	9781424411092
DOI	10.1109/ISCE.2007.4382173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Image coding Image storage Streaming media Fourier transforms Discrete cosine transforms Image communication Propagation losses Network servers Web server image compression architecture design VLSI implementation cellular automata re-configurable 2-D CAT/ICAT
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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