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A New Register Allocation Scheme for Low Power Data Format Converters
| Content Provider | Semantic Scholar |
|---|---|
| Author | Srivatsan, Kala Chakrabarti, Chaitali Lucke, Lori E. |
| Copyright Year | 2007 |
| Abstract | In many applications, such as digital signal processing, data format converters are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize data format converter architectures while optimizing the number of registers used to store the data. In this paper, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the data format converter. Low power data format converters are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows signiicant improvement over previous techniques. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://enws155.eas.asu.edu:8001/jourpapers/kala.ps |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Analog-to-digital converter Architecture as Topic Converter Device Component Digital signal processing Heuristic Integer (number) Integer programming Linear programming formulation Processor register Register allocation |
| Content Type | Text |
| Resource Type | Article |
