NDLI: A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation

Content Provider	IEEE Xplore Digital Library
Author	Jie Guo Jun Liu Mennenga, B. Fettweis, G.P.
Copyright Year	2007
Description	Author affiliation: Dresden Univ. of Technol., Dresden (Jie Guo; Jun Liu; Mennenga, B.; Fettweis, G.P.)
Abstract	This paper starts with the introduction of the Synchronous Transfer Architecture (STA), a new variant of VLIW architecture which can be viewed as a version of Transport-Triggered Architectures (TTA). Since the quality of assembly code generated by traditional high-level language compiler for such architectures is not satisfactory, we propose a novel phase-coupled compiler, in which the instruction selection and register allocation are solved together by using a two-step register allocator. According to our studies, this approach can reduce both execution time and size of the generated code by about 40%-60% in comparison to code assembled by conventional (phase-separated) compilers. Moreover, assembly code quality achieved by using two-step register allocation is comparable to the code quality obtained by a phase-coupled compiler backend based on Integer Linear Programming which requires much longer compilation time.
Starting Page	346
Ending Page	352
File Size	503865
Page Count	7
File Format	PDF
ISBN	9781424410262
ISSN	21600511
DOI	10.1109/ASAP.2007.4459288
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-09
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Registers Assembly Processor scheduling Optimization methods Integer linear programming Digital signal processing Hardware Mobile communication High level languages
Content Type	Text
Resource Type	Article

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