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Design and Implementation of Diminished-one modulo 2 N + 1 Adder Using Fpga Technology
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2015 |
| Abstract | -Two modified architectures for modulo 2+1 adders are introduced in this paper. Only some of the carries of modulo 2+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing stage and carry select blocks are combine the multiplexer operation of a diminishedone adder can be implemented in smaller LUT’s and less consumes power, while maintain the same operating speed and delay. The modulo adder 2+1 adders can be easily derived by adding extra logic of modulo 2-1 adders present in second architecture. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijpres.com/pdf18/4.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
