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Diminished-One Modulo 2n + 1 Adder Design (2002)
| Content Provider | CiteSeerX |
|---|---|
| Author | Vergos, Haridimos T. Efstathiou, Costas Nikolos, Dimitris |
| Abstract | Abstract—This paper presents two new design methodologies for modulo 2n 1 addition in the diminished-one number system. The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. VLSI realizations of the proposed circuits in a standard-cell technology are utilized for quantitative comparisons against the existing solutions. Our results indicate that the proposed carry look-ahead adders are area and time efficient for small values of n, while for the rest values of n the proposed parallel-prefix adders are considerably faster than any other already known in the open literature. Index Terms—Modulo 2n 1 addition, carry look-ahead addition, parallel-prefix adders, diminished-one number representation, VLSI adders. æ 1 |
| File Format | |
| Journal | IEEE Trans. Comput |
| Language | English |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
