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Design and Implementation of modulo Adder Using Verilog Hdl in Fpga Technology
| Content Provider | Semantic Scholar |
|---|---|
| Author | Rajashekar, Rakshith Swamy, Burra Ayyappa |
| Copyright Year | 2014 |
| Abstract | Modulo of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs for modulo(2n ± 1) adders have rendered the latency of such adders quite competitive with ordinary adders. The next logical step is to approach the problem in a unified and systematic manner that does not require each design to be taken up from scratch and to undergo the error-prone and labor-intensive optimization for high speed and low power dissipation. Accordingly, we devise a new redundant representation of mod-(2n ± 1) residues that allows ordinary fast adders and a small amount of peripheral logic to be used for mod-(2n ± 1) addition. Advantages of the building-block approach include shorter design time, easier exploration of the design space (area/speed/power tradeoffs), and greater confidence in the correctness of the resulting circuits. Advantages of the unified design include the possibility of faulttolerant and gracefully degrading RNS circuit realizations with fairly low hardware redundancy. Keywords— Modulo adder, parallel-prefix computation,VLSI design. INTRODUCTION The modulo 2n+1 adder has the applications in many fields, say pseudorandom number generation, cryptography, convolution computations without round-off errors. It has the applications in residue number system (RNS) also. The RNS is an arithmetic system which decomposes a number into parts (residues) and performs arithmetic operations in parallel for each residue without the need of carry propagation between them, which leads to significant speed-up over the corresponding binary operations. RNS is well suited to applications that are rich of addition/subtraction and multiplication operations and has been adopted in the design of digital signal processors, FIR filters and communication components, offering in several cases apart from enhanced operation speed and low power characteristics. There are three input representations chosen for the input operands namely, the normal weighted one, the diminished-1 and the signed-LSB representations. But, only the first two representations in the following are considered, since the adoption of the signedLSB representation does not lead to more efficient circuits in delay or area terms. The input operands and results are limited between 0 and Volume 3, Issue 1 OCT 2014 IJRAET 2n when performing arithmetic operations modulo 2n + 1. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijraet.com/pdf7/5.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
