NDLI: Enabling 22-nm Logic Node with Advanced RET Solutions

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Enabling 22-nm Logic Node with Advanced RET Solutions

Content Provider	Semantic Scholar
Author	Farysa, V. Depreb, L. Findersc, J. Arnouxb, V. Trouillera, Y. Liub, Huaxiang Yesiladaa, E. Zeggaouia, N. Alleaumea, C. Monnet, Rue Jean
Copyright Year	2011
Abstract	The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the art scanner will be limited to a numerical aperture of 1.35. Thus we cannot “simply” apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions in order to maintain the 50% density gain imposed by the Moore’s law. One of the most challenging parts to enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is clearly established that early process for these layers will be performed by double patterning technique coupled with advanced OPC solutions.
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://brion.com/wordpress/wp-content/uploads/2010/08/Enabling-22-nm-Logic.pdf
Language	English
Access Restriction	Open
Subject Keyword	Anatomic Node Circuit complexity Control display unit Debian Elegant degradation Etching (microfabrication) Fused filament fabrication Greater Than Jog dial Jogging Mathematical optimization Moore's law Node - plant part Numerical analysis Numerical aperture Open Platform Communications Overlay Device Component Physical vapor deposition Resolution enhancement technology Rule (guideline) Scanner Device Component Semiconductor device fabrication Semiconductor industry Solutions Spacer Device Component Spatial variability anatomical layer
Content Type	Text
Resource Type	Article

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