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Modeling Techniques for Strained CMOS Technology
| Content Provider | Semantic Scholar |
|---|---|
| Author | Selberherr, Siegfried |
| Copyright Year | 2009 |
| Abstract | Downscaling of MOSFETs as institutionalized by Moore's law is successfully continuing because of innovative changes in the technological processes and the introduction of new materials. The 32nm MOSFET process technology recently developed by Intel [1] involves new hafnium-based high-k dielectric/metal gates and represents a major change in the technological process since the invention of MOSFETs. Although alternative channel materials with a mobility higher than in Si were already investigated, it is commonly believed that strained Si will be the main channel material even for MOSFETs beyond the 32nm technology node. With scaling apparently approaching its fundamental limits, the semiconductor industry is facing critical challenges. New engineering solutions and innovative techniques are required to improve CMOS device performance. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.iue.tuwien.ac.at/pdf/ib_2009/CP2009_Sverdlov_16.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Anatomic Node CMOS Downscaling Hafnium High-κ dielectric Image scaling Moore's law Semiconductor device fabrication Semiconductor industry Solutions |
| Content Type | Text |
| Resource Type | Article |
