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Design and Analysis of Dynamic Comparator with Reduced Power and Delay
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shekhar, S. Murthy Sinha, Sachidananda |
| Copyright Year | 2015 |
| Abstract | The need for low-power and high speed analog-to-digital converters is pushing toward the use of dynamic comparators to maximize speed and power efficiency. In this paper, performances of various types of the dynamic comparators are being compared in terms of speed, delay and power. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional comparator is modified for low-power and fast operation even in small supply voltages. It is shown that in the proposed dynamic comparator both the power consumption and delay time are reduced. The circuits are simulated using TANNER tool with 0.18μm technology and supply voltage 1.8V. Keyword: Preamplifier, Kickback noise, Dynamic Latch Comparator, Transmission Gate, Parasitic Node Capacitance. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijsr.net/archive/v4i11/NOV151349.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Analog Analog-to-digital converter Arabic numeral 0 Comparator Device Component Detectors Electric Capacitance Keyword Latch Device Component Low-power broadcasting Performance per watt Preamplifier Device Component Sensor Simulation Transmission gate voltage |
| Content Type | Text |
| Resource Type | Article |
