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Low Power SAR-ADC in 0 . 18 μm Mixed-Mode CMOS Process for Biomedical Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Jyothirmayi |
| Copyright Year | 2013 |
| Abstract | This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications.For low-power applications designer needs to come up with a compromise among speed, resolution and speed power.To reduce energy consumption, a charge redistribution technique is used along with auto zero technique for comparator offset cancellation.The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC.ADC is designed in 0.18μm CMOS technology in such a way that the total power is minimized while medium sampling rate and 8 bit resolution are achieved. IndexTerms: Analog-to-digital converters (ADCs), CMOS analog integrated circuits, low power, offset,autozero,low supply voltage, successive approximation. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://iosrjournals.org/iosr-jvlsi/papers/vol3-issue1/E0312935.pdf?id=6679 |
| Alternate Webpage(s) | http://www.iosrjournals.org/iosr-jvlsi/papers/vol3-issue1/E0312935.pdf?id=7335 |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | 8-bit Alzheimer's Disease Assessment Scale-Cognitive CDISC Version Questionnaire Analog Analog-to-digital converter Arabic numeral 0 CMOS Comparator Device Component Converter Device Component Differential nonlinearity Digital-to-analog converter Integrated circuit Latch Device Component Least significant bit Low-power broadcasting Mixed-signal integrated circuit NMOS logic Non-monotonic logic Nonlinear system PMOS logic Sampling (signal processing) Sampling - Surgical action Simulation Successive approximation ADC Transistor Very-large-scale integration voltage |
| Content Type | Text |
| Resource Type | Article |
