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Design of an FFT/IFFT Processor for MIMO OFDM Systems
| Content Provider | Semantic Scholar |
|---|---|
| Author | Raman, Chandrasekharan Madhusudhanan, R. |
| Copyright Year | 2009 |
| Abstract | In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multipleoutput orthogonal fre-quency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1–4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13m single-poly and eight-metal CMOS process. The core area is an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 s meeting IEEE 802.11n standard requirements. |
| Starting Page | 26 |
| Ending Page | 32 |
| Page Count | 7 |
| File Format | PDF HTM / HTML |
| DOI | 10.20894/IJMSR.117.001.001.005 |
| Alternate Webpage(s) | http://ijmsr.org/admin/selected/IJMSR-2009-05IJMSR-2009-05.pdf |
| Alternate Webpage(s) | https://doi.org/10.20894/IJMSR.117.001.001.005 |
| Volume Number | 1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
