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A 90-nm CMOS 800 MHz 2$$\times$$×VDD output buffer with leakage detection and output current self-adjustment
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wang, Chua-Chin Tsai, Tsung-Yi |
| Copyright Year | 2018 |
| Abstract | This work presents a 800 MHz 2$$\times$$×VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 $$\times$$× 0.439 mm$$^2$$2, and the power consumption is 68.9/98.5 ($$\upmu$$μW/MHz) at 450/800 MHz, respectively. |
| Starting Page | 343 |
| Ending Page | 350 |
| Page Count | 8 |
| File Format | PDF HTM / HTML |
| DOI | 10.1007/s10470-018-1285-3 |
| Alternate Webpage(s) | http://vlsi.ee.nsysu.edu.tw/html/papers/Journal/J_132.pdf |
| Alternate Webpage(s) | https://doi.org/10.1007/s10470-018-1285-3 |
| Volume Number | 97 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
