NDLI: 450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process

Please wait, while we are loading the content...

2015 International Conference on IC Design & Technology (ICICDT)

2014 IEEE International Conference on IC Design & Technology

Proceedings of 2013 International Conference on IC Design & Technology (ICICDT)

2012 IEEE International Conference on IC Design & Technology

2011 IEEE International Conference on IC Design & Technology

2010 IEEE International Conference on Integrated Circuit Design and Technology

Table of content

High-speed links for memory interface

Impact of resistance drift on multilevel PCM design

Dual ferroelectric capacitor architecture and its application to TAG RAM

ESD challenges in advanced CMOS systems on chip

ESD protection for wideband RF CMOS LNAs

ESD protection design for differential low-noise amplifier with cross-coupled SCR

Advanced ESD power clamp design for SOI FinFET CMOS technology

Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology

New transient detection circuit for electrical fast transient (EFT) protection design in display panels

450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process

Fully depleted Silicon-On-Insulator with back bias and strain for low power and high performance applications

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits

The $power7^{TM}$ processor SoC

MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR

A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

Voltage scaling and body biasing methodology for high performance hardwired LDPC

Pre-existing and process induced defects in high-k gate dielectrics ∼direct observation with EBIC and impact on 1/f noise∼

Reliability concerns in High-K/Metal gate technologies

Modeling the effects of plasma-induced physical damage on subthreshold leakage current in scaled MOSFETs

Design solutions for preventing process induced ESD damage during manufacturing of interconnects

Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

3D integration: Advantages, enabling technologies & applications

Direct bonding for wafer level 3D integration

Through-Silicon-Via stress 3D modeling and design

Progress and challenges of tungsten-filled through-silicon via

CAD for double patterning lithography

Fast Monte Carlo method via reduced sample number and node filtering

Computing delay correlations in SSTA

A top-down approach for substrate noise assessment flow in mixed-signal and SOC designs

Overlay-aware interconnect yield modeling in double patterning lithography

A high resolution on-chip beat frequency detection system for measuring BTI, HCI, and TDDB

Narrowing the margins with elastic clocks

Design approach to improve thermo-mechanical reliability for high-integrated passive circuits

Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current

Energy efficient power MOSFETs

A high-efficiency DC-DC buck converter for sub-3×VDD power supply

Smart power IC simulation of substrate coupled current due to majority and minority carriers transports

Emerging screen technologies impact on application engine IC power

Low power technology/circuit co-development for advanced mobile devices

Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

A robust latch-type sense amplifier using adaptive latch resistance

Power switch optimization and sizing in 65nm PD-SOI considering supply voltage noise

Tunneling-based devices and circuits

Progress on single-electron transistors

Multi-walled carbon nanotube impedance

Novel SER standards: Backgrounds and methodologies

Design techniques for soft-error mitigation

Reflections on a SER-aware design flow

Alpha-emitter induced soft-errors in CMOS 130nm SRAM: Real-time underground experiment and Monte-Carlo simulation

Cost effective soft error mitigation for parallel adders by exploiting inherent redundancy

A 60GHz receiver with 13GHz bandwidth for Gbit/s wireless links in 65nm CMOS

Dynamic biasing techniques for RF power amplifier linearity and efficiency improvement

A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output

A low power 5 MS/s 14 bit switched capacitors digital to analog converter

A new method for performance control of a differential active inductor for low power 2.4GHz applications

Improvement of integrated dipole antenna performance using diamond for intra-chip wireless interconnection

Simplified parameter extraction method for modeling on-chip spiral inductors

2009 IEEE International Conference on IC Design and Technology

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

2007 IEEE International Conference on Integrated Circuit Design and Technology

2006 IEEE International Conference on IC Design and Technology

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process

Content Provider	IEEE Xplore Digital Library
Author	Chua-Chin Wang Ron-Chi Kuo Jen-Wei Liu
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering National Sun Yat-Sen University, Kaohsiung, Taiwan (Chua-Chin Wang; Ron-Chi Kuo; Jen-Wei Liu)
Abstract	A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.
Starting Page	55
Ending Page	58
File Size	1761258
Page Count	4
File Format	PDF
ISBN	9781424457731
e-ISBN	9781424457755
DOI	10.1109/ICICDT.2010.5510290
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-02
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Leakage current Logic Detectors CMOS process Voltage control Diodes CMOS technology CMOS integrated circuits Energy consumption Signal generators gate-oxide reliability mixed-voltage-tolerant I/O buffer floating N-well circuit
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in