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Tutorial 3: Optimization Techniques for Low Power VLSI Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 1995 |
| Abstract | Srinivas Devadas will describe the power dissipation model underlying the optimization methods, and provide background in power estimation. Optimizations to reduce power dissipation at the circuit level will be presented, including transistor reordering and transistor sizing. Transformations to reduce the power dissipation of combinational logic, low-power-driven logic optimization algorithms based on these transformations, and techniques to optimize sequential logic for low power will be described. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.computer.org/web/csdl/index/-/csdl/proceedings/iccad/1995/7213/00/7213xxv.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
