Glitch power minimization techniques in low power vlsi circuits.

Article

Low power glitch free modeling in vlsi circuitry using feedback resistive path logic.

Minimization of energy dissipation in glitch free and cascadable adiabatic logic circuits

Article

Total power minimization in glitch-free cmos circuits considering process variation.

Total power minimization in glitch-free cmos circuits considering process variation (2008).

A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits

Article

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Article

A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits

Article

GFCG: Glitch free combinational clock gating approach in nanometer VLSI circuits

Article