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Power Minimisation Techniques for Testing Low Power VLSI Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Nicolici, N. Al-Hashimi, Bashir M. |
| Copyright Year | 2000 |
| Abstract | Power dissipation has becomea significant concern in deep submicron VLSI and a substantial amount of research has been conducted in order to develop power minimisation techniques. While many techniques have investigated power minimisation during the functional mode of operation, an emerging research area is power minimisation during testing. Power minimisation during test application is important since it increases yield and reliability. This paper presents a review of power minimisation techniques for testing low power VLSI circuits recently proposed by the authors. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.bib.ecs.soton.ac.uk/data/4937/pdf/nicola00.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
