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The Design and Implementation of an Asynchronous RISC Microprocessor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Zacher, Raanan Kivelevich-Carmi, Raz |
| Copyright Year | 2000 |
| Abstract | In a wide range of computer controlled systems the issue of security is often of vital importance. System developers invest a vast amount of effort in trying to create a secure system while hackers invest a great deal in trying to breach this security. Many methods of violating security have been devised. Recently, a clever method, based on inserting spurious signals into the clock line of a microprocessor that enabled secure data to be extracted from the system, was discovered. Several different approaches could be taken to tackle this problem. After some consideration it was decided that eliminating the clock from the system could be a very successful solution to the problem. The aim of this project was to design, simulate, implement and test an 8-bit asynchronous RISC microprocessor. The chip was designed over a period of 3 months and was submitted for fabrication at CMP in France. It was designed using a 3 metal 0.6u CMOS process, the die was pad limited with a size of 3.6 X 3.6 sq. mm. Timing simulations show that the chip should have a maximum throughput equivalent to about 100MIPS. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://webee.technion.ac.il/vlsi/Upload/Papers/raz_raanan2000.pdf |
| Alternate Webpage(s) | http://webee.technion.ac.il/laboratories/vlsi/Upload/Papers/raz_raanan2000.pdf |
| Alternate Webpage(s) | http://eeprojects.technion.ac.il/Kasher/2000/2000VLSI.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
