Design of modified shannon based full adder cell using ptl logic for low power applications.

Novel shannon based full adder architecture low power nueral network applications.

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Efficient Design of Low Power ALU using PTL-GDI Logic Full Adder

Low Power Delay Product Full Adder Design Using Pasta and PTL CMOS Logic

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Evaluation of power delay product for low power full adder circuits based on gdi logic cell using mentor graphics.

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Design of Controlled Adder / Subtractor Cell Using Shannon Based Full Adder

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Low power-area gdi & ptl techniques based full adder designs.

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Low-Power High-Speed Double Gate 1-bit Full Adder Cell

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Low-Power 1-Bit Full-Adder Cell Using Modified Pass Transistor Logic

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