Loading...
Please wait, while we are loading the content...
Similar Documents
Low-Power 1-Bit Full-Adder Cell Using Modified Pass Transistor Logic
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2013 |
| Abstract | Adders have become one of the important components in the digital world in such a way that there is no design without it. Adders are not only used for additions, but also used in many other functions like Subtractions, Multipliers, and Dividers etc. In the field of Very Large Scale Integration (VLSI), Adders are used as the basic component from processors to ASIC’s. Hence a well optimized Adder design is needed. Propagation delay, Power and Area are the acceptable Quality metrics of the designed products. Recent days has proved that the use of Complementary Pass Transistor Logics (CPL) has provided a drastic reduction in the power compared to CMOS logic. This paper has spread the focus on Low power Adder design based on PTL’s and achieved 2.5% reduction in power without affecting other quality metrics of the design. The design has been modelled and analyzed using TANNER EDA with TSMC MOSIS 250nm technology. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijcsit.com/docs/Volume%204/vol4Issue3/ijcsit2013040324.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
