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Low Power Delay Product Full Adder Design Using Pasta and PTL CMOS Logic
| Content Provider | Semantic Scholar |
|---|---|
| Author | Varshalakshmi, S. Kasiselvanathan, M. Sandhiya, N. Ruvedha, K. Nandhini, G. |
| Copyright Year | 2016 |
| Abstract | The design of Full Adder circuit using Multiplexer (Mux) based Parallel self-Timed Adder (PASTA) and Mux based Pass Transistor Logic (PTL) is designed using CMOS. Both the adder circuits are implemented in 130-nm CMOS technology process which aims at the current flows from source to drain should be high. The power, delay and the power delay product (PDP) are obtained by using T-spice simulation. The simulation results show that the Mux based PTL adder circuit provides lower PDP than the Mux based PASTA adder circuit. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijcns.com/pdf/ijtesvol8no22016-4.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
