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An Area-Efficient Carry Select Adder Design by using 180 nm Technology
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wadhwa, Garish Kumar Grover, Amit Grover, Neeti Singh, Gurpreet |
| Copyright Year | 2013 |
| Abstract | In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960. |
| File Format | PDF HTM / HTML |
| DOI | 10.14569/IJACSA.2013.040118 |
| Volume Number | 4 |
| Alternate Webpage(s) | http://thesai.org/Downloads/Volume4No1/Paper_18-An_Area-Efficient_Carry_Select_Adder_Design_by_using_180_nm_Technology.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
