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Design of Power Efficient Multiplier using area delay power efficient carry select adder
| Content Provider | Semantic Scholar |
|---|---|
| Author | Babu, Aluri Bulli Reddy, Gaddam Sekhar Babu, Sannikanti Kishore |
| Copyright Year | 2016 |
| Abstract | Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the area, time and power efficient carry select adder. A fast carry select adder is used for the final two-operand adder In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. |
| Starting Page | 64 |
| Ending Page | 67 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| Volume Number | 6 |
| Alternate Webpage(s) | https://works.bepress.com/kiratpalsingh/57/download/ |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
